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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD7675 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 16-bit, 100 ksps, differential adc functional block diagram control logic and calibration circuitry clock ob/ 2c 16 data[ 15:0] busy cs ser/ par ognd ovdd dgnd dvdd serial port p arallel interface byteswap rd av d d a gnd ref refgnd pd reset cnvst in switched cap dac AD7675 in+ pulsar selection type/ksps 100?50 500?70 1000 pseudo ad7660 ad7650 differential ad7664 true bipolar ad7663 ad7665 ad7671 true differential AD7675 ad7676 ad7677 features throughput: 100 ksps inl: 1.5 lsb max ( 0.0015% of full scale) 16 bits resolution with no missing codes s/(n+d): 94 db typ @ 45 khz thd: ?10 db typ @ 45 khz differential input range: 2.5 v both ac and dc specifications no pipeline delay parallel (8 bits/16 bits) and serial 5 v/3 v interface spi/qspi/microwire/dsp compatible single 5 v supply operation 15 mw typical power dissipation, 15 w @ 100 sps power-down mode: 7 w max packages: 48-lead quad flatpack (lqfp), 46-lead frame chip scale (lfcsp) pin-to-pin compatible with the ad7660 replacement of ad676, ad677 applications ct scanners data acquisition instrumentation spectrum analysis medical instruments battery-powered systems process control general description the AD7675 is a 16-bit, 100 ksps, charge redistribution sar, fully differential analog-to-digital converter that operates from a single 5 v power supply. the part contains a high speed 16-bit sampling adc, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. the AD7675 is hardware factory calibrated and is comprehensively tested to ensure such ac parameters as signal-to-noise ratio (snr) and total harmonic distortion ( thd), in addition to the more traditional dc parameters of gain, offset, and linearity. it is fabricated using analog devices? high performance, 0.6 micron cmos process and is available in a 48-lead lqfp or a tiny 48-lead lfcsp with operation specified from 40 c to +85 c. product highlights 1. excellent inl the AD7675 has a maximum integral nonlinearity of 1.5 lsb with no missing 16-bit code. 2. superior ac performances the AD7675 has a minimum dynamic of 92 db, 94 db typi cal. 3. fast throughput the AD7675 is a 100 ksps, charge redistribution, 16-bit sar adc with internal error correction circuitry. 4. single-supply operation the AD7675 operates from a single 5 v supply and typically dissi pates only 17 mw. its power dissipation decreases with the throughput to, for instance, only 15 w at a 100 sps throughput. it consumes 7 w maximum when in power-down. 5. serial or parallel interface versatile parallel (8 bits or 16 bits) or 2-wire serial interface arrangement compatible with either 3 v or 5 v logic. * patent pending spi and qspi are trademarks of motorola inc. microwire is a trademark of national semiconductor inc.
rev. a e2e AD7675especifications parameter conditions min typ max unit resolution 16 bits analog input voltage range v in+ e v ine ev ref +v ref v operating input voltage v in+, v ine to agnd e0.1 +3 v analog input cmrr f in = 10 khz 79 db input current 100 ksps throughput 1 a input impedance see analog input section throughput speed complete cycle 10 s throughput rate 0 100 ksps dc accuracy integral linearity error e1.5 +1.5 lsb 1 no missing codes 16 bits transition noise 0.35 lsb +full-scale error 2 e22 +22 lsb efull-scale error 2 e22 +22 lsb zero error 2 e8 +8 lsb power supply sensitivity avdd = 5 v 5% 0.5 lsb ac accuracy signal-to-noise f in = 20 khz 92 94 db 3 f in = 45 khz 94 db 3 spurious free dynamic range f in = 20 khz 104.5 110 db 3 f in = 45 khz 110 db 3 total harmonic distortion f in = 20 khz e110 e103.5 db 3 f in = 45 khz e110 db 3 signal-to-(noise+distortion) f in = 20 khz 92 94 db 3 f in = 45 khz 94 db 3 f in = 45 khz, e60 db input 34 db 3 e3 db input bandwidth 3.9 mhz sampling dynamics aperture delay 2ns aperture jitter 5 ps rms transient response full-scale step 8.75 s reference external reference voltage range 2.3 2.5 avdd e 1.85 v external reference current drain 100 ksps throughput 35 a digital inputs logic levels v il e0.3 +0.8 v v ih 2.0 dvdd + 0.3 v i il e1 +1 a i ih e1 +1 a digital outputs data format parallel or serial 16-bit conversion results available pipeline delay immediately after completed conversion v ol i sink = 1.6 ma 0.4 v v oh i source = e100 a ovdd e 0.6 v power supplies specified performance avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 5.25 4 v operating current 300 ksps throughput avdd 3ma dvdd 5 750 a ovdd 5 7.5 a power dissipation 5 100 ksps throughput 17 25 mw 100 sps throughput 15 w in power-down mode 5 7 w temperature range 7 specified performance t min to t max e40 +85 c notes 1 lsb means least significant bit. with the 2.5 v input range, one lsb is 76.3 v. 2 see definition of specifications section. these specifications do not include the error contribution from the external referenc e. 3 all specifications in db are referred to a full-scale input fs. tested with an input signal at 0.5 db below full-scale unless o therwise specified. 4 the max should be the minimum of 5.25 v and dvdd + 0.3 v. 5 tested in parallel reading mode. 6 with ovdd below dvdd + 0.3 v and all digital inputs forced to dvdd or dgnd, respectively. 7 contact factory for extended temperature range. specifications subject to change without notice. (e40 c to +85 c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted.)
rev. a e3e AD7675 timing specifications symbol min typ max unit refer to figures 11 and 12 convert pulsewidth t 1 5ns time between conversions t 2 10 s cnvst shihd shihasr 2 ac ad 2 csd ct 2 at rstp rpi cnvst datavd 2 datavsd ardatav 2 rt rsi cs sncvd cs iscvd cs sdtd cnvst sncd 2 sncascd 2 iscp 2 2 ischih 2 2 2 isc 2 2 sdtvst 2 22 sdtvht 2 2 2 scsncd 2 2 cs hihsnchi 2 cs hihischi 2 cs hihsdthi 2 shihsrac 2 2 sti cnvst sncad 2 2 sncdsd 2 rssi scst scasdtd 2 sdinst sdinht scp 2 schih sc nts isncscsdtc 2 isti s c cavdddvdd vvdd2v2v
rev. a AD7675 e4e table i. serial clock timings in master read after convert divsclk[1] 0011 divsclk[0] 0101 unit sync to sclk first edge delay minimum t 18 3171 717ns internal sclk period minimum t 19 25 50 100 200 ns internal sclk period typical t 19 40 70 140 280 ns internal sclk high minimum t 20 12 22 50 100 ns internal sclk low minimum t 21 7214 999ns sdout valid setup time minimum t 22 4181 818ns sdout valid hold time minimum t 23 24308 9ns sclk last edge to sync delay minimum t 24 360 140 300 ns busy high width maximum t 28 2 2.5 3.5 5.75 s absolute maximum ratings 1 analog inputs in+ 2 , ine 2 , ref, refgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . avdd + 0.3 v to agnd e 0.3 v ground voltage differences agnd, dgnd, ognd . . . . . . . . . . . . . . . . . . . . . 0.3 v supply voltages avdd, dvdd, ovdd . . . . . . . . . . . . . . . . e0.3 v to +7 v avdd to dvdd, avdd to ovdd . . . . . . . . . . . . . . 7 v dvdd to ovdd . . . . . . . . . . . . . . . . . . . . . e0.3 v to +7 v digital inputs . . . . . . . . . . . . . . . . e0.3 v to dvdd + 0.3 v internal power dissipation 3 . . . . . . . . . . . . . . . . . . . . 700 mw internal power dissipation 4 . . . . . . . . . . . . . . . . . . . . . . 2.5 w junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 c storage temperature range . . . . . . . . . . . . e65 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 see analog input section. 3 specification is for device in free air: 48-lead lqfp: ja = 91 c/w, jc = 30 c/w. 4 specification is for device in free air: lfcsp: ja = 26 c/w to output pin c l 60pf 1 500 a i oh 1.6ma i ol 1.4v in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10pf; otherwise, the load is 60pf maximum. note 1 figure 1. load circuit for digital interface timing, sdout, sync, sclk outputs, c l = 10 pf 0.8v 2v 2v 0.8v t dela y 2v 0.8v t delay figure 2. voltage reference levels for timing caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7675 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide package model temperature range package description option AD7675ast e40 c to +85 c quad flatpack (lqfp) st-48 AD7675astrl e40 c to +85 c quad flatpack (lqfp) st-48 AD7675acp e40 c to +85 cc hip scale (lfcsp) cp-48 AD7675acprl e40 c to +85 cc hip scale (lfcsp) cp-48 eval-AD7675cb 1 evaluation board eval-control brd2 2 controller board notes 1 this board can be used as a stand-alone evaluation board or in conjunction with the eval-control brd2 for evaluation/ demonstration purposes. 2 this board allows a pc to control and communicate with all analog devices evaluation boards ending in the cb designators.
rev. a AD7675 e5e pin function descriptions pin no. mnemonic type description 1 agnd p analog power ground pin 2 avdd p input analog power pins. nominally 5 v. 3, 6, 7, nc no connect 40e42, 44e48 4 byteswap di parallel mode selection (8-bit/16-bit). when low, the lsb is output on d[7:0] and the msb is output on d[15:8]. when high, the lsb is output on d[15:8] and the msb is output on d[7:0]. 5ob/ 2c di stc 2c hih s sr par di spsihih data data d ppdsr par hih 2 data2 di sr par 2p p d divsc sr par hiht int rdcsdin t i data di sr par ppd t int sr par hih t int sct int hihz sc data di sr par ppd invsnc sr par hih sncsnchihhihsnc data di sr par ppd invsc sr par hihsc i data di sr par ppd rdcsdin sr par hih t int t int hihrdcsdin adcsdt t sdindatasc t int rdcsdinrdc sdinhih sdt rdcsdin sdt nd p iidp vdd p iidpn vv dvdd p dpnv 2 dnd p dp
rev. a AD7675 e6e pin function descriptions (continued) pin no. mnemonic type description 21 data[8] do when ser/ par ppd sdt sr par hih zscctad stdata 2c it int sdtscit int hihi invscsdtsc iinvschihsdtsc 22 data di sr par ppd sc sr par hih t int pt sdtinvscp 2 data d sr par ppd snc sr par hih zt int invsncsnchihhih sdtinvsnchih sncsdt 2 data d sr par ppd rdrrr sr par hiht int hih i rdrrr 22 data2 d 2ppd t sr par 2 s d thihhih t s dnd p td rd di rd cs rd 2 cs di cs cs rd cs rst di rihihadc pd di pdihih cnvst di sci cnvst hih cnvst ti cnvst and p ta r ai riv rnd ai ria in ai dnai in ai dpai nts aiai didi did dd pp
rev. a AD7675 e7e definition of specifications integral nonlinearity error (inl) integral nonlinearity is the maximum deviation of a straight line drawn through the transfer function of the actual adc. the deviation is measured from the middle of each code. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. +full-scale error t he last transition (from 011 . . . 10 to 011 . . . 11 in two?s c omplement coding) should occur for an analog voltage 1 1/2 lsb b elow the nominal +full scale (+2.499886 v for the 2.5 v range). the +full-scale error is the deviation of the actual level of the last transition from the ideal level. efull-scale error t he first transition (from 100 . . . 00 to 100 . . . 01 in two?s c omplement coding) should occur for an analog voltage 1/2 lsb above the nominal efull scale (e2.499962 v for the 2.5 v range). the efull-scale error is the deviation of the actual level of the last transition from the ideal level. bipolar zero error the bipolar zero error is the difference between the ideal m idscale input voltage (0 v) and the actual voltage producing the m idscale output code. spurious free dynamic range (sfdr) the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to s/(n+d) by the following formula: enob s n d db =+ [] () /./. 176 602 and is expressed in bits. total harmonic distortion (thd) t hd is the ratio of the rms sum of the first five harmonic com ponents to the rms value of a full-scale input signal and is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal-to-(noise + distortion) ratio (s/[n+d]) s/(n+d) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n+d) is expressed in decibels. aperture delay aperture delay is a measure of the acquisition performance and is measured from the falling edge of the cnvst transintrspns tad pincniratin p st 2 2 2 2 2 2 2 2 22 2 2 2 2 2 pin idntiir tp vi ns a nd cnvst pd rst cs rd dnd a nd av d d nc tsap 2c nc nc ncncnnct sr par d d d2divsc s d d d ad ddivsc d2 nc nc nc nc nc in nc nc nc in rnd r dt int dinvsnc dinvsc drdcsdin nd vdd dvdd dnd dsdt dsc dsnc drdrrr
rev. a AD7675 e8e et ypical performance characteristics code 1.00 0 16384 32768 49152 65536 inl e lsb 0.75 0.25 0.00 e0.50 e1.00 0.50 e0.25 e0.75 tpc 1. integral nonlinearity vs. code code in hexa 9000 7ffb 0 counts 8000 6000 4000 2000 0000 7000 3000 1000 5000 7ffc 0 7ffd 0 7ffe 6 7fff 8246 8000 8118 8001 14 8002 0 8003 0 8004 0 tpc 2. histogram of 16,384 conversions of a dc input at the code transition positive inl e lsb 18 0.2 number of units 14 6 0 10 2 0.4 0.6 0.8 1.0 0 16 8 12 4 tpc 3. typical positive inl distribution (40 units) code in hexa 16000 7ff9 0 counts 12000 8000 4000 0000 14000 6000 2000 10000 7ffa 0 7ffb 0 7ffc 887 7ffd 7ffe 810 7fff 0 8000 0 8001 0 8002 0 7ff8 0 14687 tpc 4. histogram of 16,384 conversions of a dc input at the code center negative inl e lsb 18 e0.8 number of units 14 6 0 10 2 e0.6 e0.4 e0.2 0.0 e1.0 16 8 12 4 tpc 5. typical negative inl distribution (40 units) frequency e khz 0 0102 030 50 amplitude e db of full scale e40 e80 e100 e140 e180 e60 e120 e160 40 e20 f s = 100 ksps f in = 45.01khz snr = 94db thd = e110db sfdr = 110db sinad = 93.9db tpc 6. fft plot
rev. a e9e AD7675 frequency e khz 100 snr and s/[n+d] e db 90 70 80 10 1000 1 100 95 85 75 16.0 enob e bits 15.0 13.0 14.0 15.5 14.5 13.5 snr sinad enob tpc 7. snr, s/(n+d), and enob vs. frequency input level e db 96 snr (referred to full scale) e db 94 88 e40 0 e60 e20 92 90 snr sinad e50 e30 e10 tpc 8. snr and s/(n+d) vs. input level temperature e c 96 snr e db 84 90 0 125 e55 85 93 87 snr thd e35 45 105 25 e15 65 e104 thd e db e112 e108 e106 e110 tpc 9. snr, thd vs. temperature c l e pf 50 t 12 delay e ns 0 20 200 0 40 10 100 50 150 30 ov dd = 5.0v @ 25 c ov dd = 5.0v @ 85 c ov dd = 2.7v @ 25 c ov dd = 2.7v @ 85 c tpc 10. typical delay vs. load capacitance c l sampling rate e sps operating currents e a 0.001 0.1 10 100 0.01 1k 100 10k 1 100k 10 1k 10k 100k dvdd ovdd av d d tpc 11. operating currents vs. sample rate temperature e c 250 power-down operating currents e na 0 100 e15 105 e55 45 150 50 dvdd e35 5 85 25 65 200 ovdd av d d tpc 12. power-down operating currents vs. temperature
rev. a AD7675 e10e in+ ref refgnd ine 32,768c 16,384c msb 4c 2c c c lsb sw + switches control 32,768c 16,384c msb 4c 2c c c lsb sw e busy output code cnvst control logic comp figure 3. adc simplified schematic circuit information the AD7675 is a fast, low power, single-supply, precise 16-bit analog-to-digital converter (adc). the AD7675 is capable of converting 100,000 samples per second (100 ksps) and allows power saving between conversions. when operating at 100 sps, for example, it consumes typically only 15 w. this feature makes the AD7675 ideal for battery-powered applications. the AD7675 provides the user with an on-chip track/hold, successive approximation adc that does not exhibit any pipe- line or latency, making it ideal for multiple multiplexed channel applications. the AD7675 can be operated from a single 5 v supply and be interfaced to either 5 v or 3 v digital logic. it is housed in a 48- lead lqfp package that combines space savings and allows flexible configurations as either serial or parallel interface. the AD7675 is pin-to-pin compatible with the ad7660. converter operation the AD7675 is a successive approximation analog-to-digital converter based on a charge redistribution dac. figure 3 shows the simplified schematic of the adc. the capacitive dac con- sists of two identical arrays of 16 binary-weighted capacitors that are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the comparator?s input are connected to agnd via sw + and sw e . all independent switches are connected to the analog inputs. thus, the capacitor arrays are used as sampling capacitors and acquire both analog signals. when the acquisition phase is complete and the cnvst s s t rnd t inin rndr v r 2v r v r t s a adcs t 2c ad t ad anainpt ss s s ss s ss adccds adcit tpratr c s 2 2 s st s tpc dt
rev. a AD7675 e11e typical connection diagram figure 5 shows a typical connection diagram for the AD7675. different circuitry shown on this diagram is optional and is discussed below. analog inputs figure 6 shows a simplified analog input section of the AD7675. in+ ine a gnd av d d r+ = 684 c s c s re = 684 figure 6. simplified analog input the diodes shown in figure 6 provide esd protection for the inputs. care must be taken to ensure that the analog input sig- nal never exceeds the absolute ratings on these inputs. this will cause these diodes to become forward-biased and start conducting current. these diodes can handle a forward-biased current of 120 ma maximum. this condition could eventually occur when the input buffer?s (u1) or (u2) supplies are different from avdd. in such a case, an input buffer with a short-circuit current limitation can be used to protect the part. this analog input structure is a true differential structure. by using these differential inputs, signals common to both inputs are rejected, as shown in figure 7, which represents the typical cmrr over frequency. frequency e hz cmrr e db 45 75 10k 10m 1k 1m 80 65 100k 55 85 70 60 50 40 figure 7. analog input cmrr vs. frequency av d d a gnd dgnd dvdd ovdd ognd ser/ par cnvst busy sdout sclk rd cs reset pd refgnd c ref 2.5v ref note 1 ref 100 d clock AD7675 c/ p/dsp serial port digital supply (3.3v or 5v) analog supply (5v) dvdd ob/ 2c note 7 byteswap dvdd 50k 100nf 1m in+ analog input+ c c 2.7nf u1 note 4 note 5 50 ad8021 e + 15 note 2 note 3 note 6 adr421 10 f 100nf + 10 f 100nf + 100nf + 10 f ine analog inpute c c 2.7nf u2 note 4 note 5 50 ad8021 e + 15 50 + 1 f notes 1. see voltage reference input section. 2. with the recommended voltage references, c ref is 47 f. see chapter voltage reference input section 3. optional circuitry for hardware gain calibration. 4. the ad8021 is recommended. see driver amplifier choice section. 5. see analog input section. 6. option, see power supply section 7. optional low jitter cnvst , see conversion control section. figure 5. typical connection diagram. ( 2.5 v range shown)
rev. a AD7675 e12e during the acquisition phase for ac signals, the AD7675 behaves like a one-pole rc filter consisting of the equivalen t resis tance r+, re, and c s . the resistors r+ and re are typically 684 and are lumped components made up of some serial resistors and the on resistance of the switches. the capacitor c s is typi cally 60 pf and is mainly the adc sampling capacitor. this one pole filter with a typical e3 db cutoff frequency of 3.9 mhz reduces undesirable aliasing effect and limits the noise coming from the inputs. because the input impedance of the AD7675 is very high, the AD7675 can be driven directly by a low impedance source without gain error. that allows users to put, as shown in figure 5, an external one-pole rc filter between the output of the amplifier output and the adc analog inputs to even further improve the noise filtering done by the AD7675 analog input circuit. however, the source impedance has to be kept low because it affects the ac performances, especially the total harmonic distortion. the maximum source impedance depends on the amount of total harmonic distortion (thd) that can be tolerated. the thd degrades proportionally to the source im pedance. single to differential driver for applications using unipolar analog signals, a single-ended to differential driver will allow for a differential input into the part. the schematic is shown in figure 8. u2 590 590 2.5v ref c c ad8021 590 AD7675 in+ ine ref 2.5v ref u1 analog input (unipolar) c c ad8021 590 figure 8. single-ended-to-differential driver circuit this configuration, when provided an input signal of 0 to v ref , will produce a differential 2.5 v with a common mode at 1.25 v. if the application can tolerate more noise, the ad8138 can be used. driver amplifier choice although the AD7675 is easy to drive, the driver amplifier needs to meet at least the following requirements: ? the driver amplifier and the AD7675 analog input circuit have to be able to settle for a full-scale step of the capaci- tor array at a 16-bit level (0.0015%). in the amplifier?s data sheet, the settling at 0.1% or 0.01% is more commonly speci- fied. it could significantly differ from the settling time at 16-bit level and, therefore, it should be verified prior to the driver selection. the tiny op amp ad8021, which combines ultra low noise and a high gain bandwidth, meets this settling time requirement even when used with a high gain up to 13. ? the noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the snr and transi- tion noise performance of the AD7675. the noise coming from the driver is filtered by the AD7675 analog input circuit one-pole, low-pass filter made by r+, re, and c s . the snr degradation due to the amplifier is: snr log fne loss db n = + 20 28 784 4 3 2 () where f ? db is the ? db input bandwidth of the AD7675 (3.9 mhz) or the cutoff frequency of the input filter if any is used. n is the noise factor of the amplifier (1 if in buffer con- figuration) e n is the equivalent input noise voltage of the op amp in nv / (hz) 1/2 . for instance, in the case of a driver with an equivalent input noise of 2 nv/ hz ad2 snr tthd ad tad2 tad2 t np tad22 tad2ad ad snr tad2 hzi 2 tad tadp2p vri tad2v trad t r rndt sr rrnd tadr2ad tadr2 tad2 ad ad
rev. a AD7675 e13e care should also be taken with the reference temperature coeffi- cient of the voltage reference which directly affects the full-scale accuracy if this parameter matters. for instance, a 15 ppm/ c tempco of the reference changes the full scale by 1 lsb/ c. v ref , as mentioned in the specification table, could be in creased to avdd e 1.85 v. the benefit here is the increased snr obtained as a result of this increase. since the input range is defined in terms of v ref , this would essentially increase the range to make it a 3 v input range with an avdd above 4.85 v. the theoretical improvement as a result of this increase in reference is 1.58 db (20 log [3/2.5]). due to the theoretical quantization noise, however, the observed improvement is ap proximately 1 db. the ad780 can be selected with a 3 v reference voltage. power supply t he AD7675 uses three sets of power supply pins: an analog 5v supply avdd, a digital 5 v core supply dvdd, and a digital input/output interface supply ovdd. the ovdd supply allows direct interface with any logic working between 2.7 v and dvdd + 0.3 v. to reduce the number of supplies needed, the digital core ( dvdd) can be supplied through a simple rc filter from the analog supply as shown in figure 5. the AD7675 is independent of power supply sequencing once ovdd does not exceed dvdd by more than 0.3 v, and thus free from supply v oltage induced latchup. additionally, it is very insensitive to power supply variations over a wide frequency range as shown in figure 9. frequency e hz 75 psrr e db 35 65 10k 10m 1k 1m 55 100k 45 70 60 50 40 figure 9. psrr vs. frequency power dissipation the AD7675 automatically reduces its power consumption at the end of each conversion phase. during the acquisition phase, the operating currents are very low, which allows a significant power saving when the conversion rate is reduced as shown in figure 10. this feature makes the AD7675 ideal for very low power battery applications. it should be noted that the digital interface remains active even during the acquisition phase. to reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power rails (i.e., dvdd and dgnd) and ovdd should not exceed dvdd by more than 0.3 v. sampling rate e sps power dissipation e w 0.1 10k 100 100k 10 10k 100 1k 1 100k 1k 10 1m figure 10. power dissipation vs. sample rate conversion control figure 11 shows the detailed timing diagrams of the conversion process. the AD7675 is controlled by the signal cnvst pd t cnvst cs rd cnvst 2 d acir cnvrt acir cnvrt s ct cnvst cnvst s cnvst s a cnvst snr cnvst s cnvst
rev. a AD7675 e14e t 9 reset data busy cnvst t 8 figure 12. reset timing for other applications, conversions can be automatically initi- ated. if cnvst sad cnvst ad i sa cnvst iad sps diitaintrac tad tt advv vddad 2c t cs rd cs ad ad rd cnvst s data s cs rd prviscnvrsindata ndata pdtr cr paraintrac tad sr par t t data s 2 s cs rd crrnt cnvrsin spdtr rc cs cnvst rd prvis cnvrsin data s 2 s spdtrr dc ttsap a sd sdtsap tsapss sdsd tsap dd cs rd t pinsd pinsd hi hi hiht t t hiht hi hi 2 2 pi
rev. a AD7675 e15e t 3 busy cs , rd cnvst sync sclk sdout 123 141516 d15 d14 d2 d1 d0 x ext/ int = 0 rdc/sdin = 0 invsclk = invsync = 0 t 14 t 20 t 15 t 16 t 22 t 23 t 29 t 28 t 18 t 19 t 21 t 30 t 25 t 24 t 26 t 27 figure 17. master serial data timing for reading (read after convert) rdc/sdin = 1 invsclk = invsync = 0 d15 d14 d2 d1 d0 x 123 141516 busy sync sclk sdout cs , rd cnvst t 3 t 1 t 17 t 14 t 15 t 19 t 20 t 21 t 16 t 22 t 23 t 24 t 27 t 26 t 25 t 18 ext/ int = 0 figure 18. master serial data timing for reading (read previous conversion during convert) serial interface the AD7675 is configured to use the serial interface when the ser/ par tad ssdttz sc astrsriaintrac ic tad sct int tad snc tscsnc t drdc sdin ad t
rev. a AD7675 e16e in read-after-conversion mode, unlike in other modes, it should be noted that the signal busy returns low after the 16 data bits are pulsed out and not at the end of the conversion phase, which results in a longer busy width. in read-during-conversion mode, the serial clock and data toggle at appropriate instances, which minimizes potential feedthrough between digital activity and the critical conversion decisions. to accommodate slow digital hosts, the serial clock can be slowed down by using divsclk. slave serial interface external clock the AD7675 is configured to accept an externally supplied serial data clock on the sclk pin when the ext/ int p i t cs cs rd t cs t a 2 ad ad t ad s s dcdrc t as cs rd ts a hz ad rdcsdin t a 2s cnvst irdcsdin sc sdths s sc cs sc sdt d d d d d s sdin invsc 2 t int rd 2 ssdtrrc
rev. a AD7675 e17e external clock data read during conversion fi gure 20 shows the detailed timing diagrams of this me thod. during a conversion, while both cs rd t s t irdrrr t rdcsdin t hz icrprcssrintracin tad t ad i a ad adct adspi adsp2adsp2 spiichc 22ad spichct ad tt t s tspispichc strcp cpcpcphaspi spispicr spcr tir irptin cnvst sdt sc d d d d d 2 s invsc cs t int rd 2 2 ssdtrrpcc s s ad 2 pstra ad dnstra rdcsdin sdt cnvst cs sc rdcsdin sdt cnvst cs sc data t scin csin cnvstin s t 2 taddcc
rev. a AD7675 e18e AD7675 * mc68hc11 * ser/ par irq miso/sdi sck i/o port busy sdout sclk cnvst ext/ int cs rd invsclk dvdd * additional pins omitted for clarity figure 22. interfacing the AD7675 to spi interface adsp-21065l in master serial interface as shown in figure 23, the AD7675 can be interfaced to the adsp-21065l using the serial interface in master mode without any glue logic required. this mode combines the advantages of reducing the wire connections and the ability to read the data during or after conversion maximum speed transfer (divsclk[0:1] both low). the AD7675 is configured for the internal clock mode (ext/ int t aadsp2 tsadsp2 tadsp 2irs crirs asrsrrst adsp2 srctadsp2sharc adsp2 adsp2 z ad adsp2 sharc sr par rs dr rc arts snc sdt sc cnvst rdcsdin rd t int cs dvdd additinapinsittdrcarit invsnc invsc 2 iadsp2 s appicatinhints tad 2h t ad t d ad adiad ad i t ad cnvst c t t tad ad d avdddvdd vdd asr adc t dvddad avdd vdd dvdd avddrc vdd dvdd tadrndand dndndr nd and adct dnd nd t tadc z adp a ad adt pc crd2
rev. a AD7675 e19e outline dimensions 48-lead plastic quad flatpack [lqfp] 1.4 mm thick (st-48) dimensions shown in millimeters top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc sq seating plane 1.60 max 0.75 0.60 0.45 view a 7 3.5 0 0.20 0.09 1.45 1.40 1.35 0.15 0.05 0.08 max coplanarity view a rotated 90 ccw pin 1 indicator 9.00 bsc sq compliant to jedec standards ms-026bbc 48-lead frame chip scale package [lfcsp] 7 mm 7 mm body (cp-48) dimensions shown in millimeters pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 bottom view 5.25 4.70 2.25 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.25 ref 0.70 max 0.65 nom 1.00 0.90 0.80 5.50 ref seating plane 0.05 max 0.02 nom coplanarity 0.60 max 0.60 max pin 1 indicator compliant to jedec standards mo-220-vkkd-2 paddle connected to agnd
e20e c02689e0e7/02(a) printed in u.s.a. rev. a revision history location page 7/02?data sheet changed from rev. 0 to rev. a. added 48-lead lfcsp to features and general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 added pulsar selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 edits to notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 additions to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edits to pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes to power supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 added 48-lead frame chip scale package (lfcsp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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